IDEA→PROTOTYPE.
From a sentence to verified silicon
Real runs against the live pipeline — natural-language spec in, synthesizable Verilog, a passing testbench, and live simulation waveforms out. Hover any clip to play.
Synchronous FIFO
A parameterizable FIFO with full/empty flags — spec to verified RTL in one pass.
8-bit ALU
Eight opcode-selected operations — arithmetic, logic, and shifts — with carry, zero, and negative flags.
PCIe Link Training (LTSSM)
A PCIe Link Training State Machine — spec to verified RTL, then simulated live with rendered waveforms.
DMA Subsystem (Hierarchical)
One complex spec, auto-decomposed into a DMA engine, FIFO, and round-robin arbiter, then generated, wired, verified end to end, and simulated live with rendered waveforms.
AXI-Lite Interconnect
Two masters arbitrating a shared AXI4-Lite bus to two slaves, with round-robin granting and address decoding, generated and verified end to end, then simulated live with rendered waveforms.
Pipelined RV32I Core
A 3-stage RISC-V pipeline with a register file, ALU, decoder, and hazard forwarding, generated and verified end to end, then simulated live with rendered waveforms.
DRAM Controller
A single-bank DRAM controller with a refresh counter, a bank state machine, and command timing, generated and verified end to end, then simulated live with rendered waveforms.
Every agent, orbiting the core
The CCX core at the center; the brain, the five generation agents, the EDA & knowledge subsystems, and the creators — the named crew who design the chip — all orbiting it. Drag to look around, scroll to zoom.