IDEA→PROTOTYPE.
Not one trick, the whole loop
Generate RTL from a sentence, watch it debug and repair its own failures, then simulate and read the waveforms, every stage in the browser, no toolchain to install.
Plain English in, verified RTL out
Describe the block in a sentence. ChipCraftX analyzes the spec, generates synthesizable Verilog, and hands back a module that already compiled clean and passed its own testbench.
- Architecture analysis before a line of RTL
- Synthesizable, parameterized Verilog
- A pass/fail verdict with the receipts
It finds its own bugs and fixes them
When a check fails, the loop reads the compile error or simulation mismatch, repairs the RTL, and re-runs, iterating until every test passes. You see the failures and the fix, not just the final file.
- Catches compile errors and simulation mismatches
- Repairs and re-verifies across iterations
- Converges on RTL that passes every check
Simulate, then read the waveforms
Open any module in the Lab, run iverilog, and inspect real VCD waveforms in the built-in viewer. Trace a signal, confirm an FSM, or chase down a timing bug, all in the browser.
- One-click iverilog simulation
- Real VCD waveforms in the Surfer viewer
- Every signal, cycle-accurate, no local tools
Talk to a specialist, not a chatbot
Switch from the pipeline to the crew and hold a real conversation. Ask Kemal to plan an architecture, have Ayumi weigh an RTL choice, or ask Mei how she’d verify a block. Each agent keeps its own history and shares your workspace.
- Kemal · architecture · Ayumi · RTL · Mei · verification · Halo · layout
- A back-and-forth with the right specialist behind the cursor
- Every agent runs on CCM-1, our own model
The crew you can call on
The same crew, where you code
ChipCraftVS brings the loop into VS Code: RTL generation, synthesis-aware diagnostics, and design chat, with nothing to leave your editor.
chipcraftx.chipcraftvs
The whole studio, docked
Design Studio, build tools (Waveform, Synthesize, Testbench, inline edit), and one-line specs, right where you code.
Verified RTL, without leaving VS Code
Describe a block; get synthesis-ready Verilog, a testbench, and a generation summary that already compiled and passed.
It debugs and fixes itself
Compile, simulate, and on a mismatch, repair and re-run, iterating in the panel until every check passes.
Real sessions, start to finish
Every clip is a real run against the live pipeline: spec in, verified RTL and live waveforms out. Hover any clip to play.
Synchronous FIFO
A parameterizable FIFO with full/empty flags. Spec to verified RTL in one pass.
8-bit ALU
Eight opcode-selected operations (arithmetic, logic, and shifts), with carry, zero, and negative flags.
PCIe Link Training (LTSSM)
A PCIe Link Training State Machine. Spec to verified RTL, then simulated live with rendered waveforms.
DMA Subsystem (Hierarchical)
One complex spec, auto-decomposed into a DMA engine, FIFO, and round-robin arbiter, then generated, wired, verified end to end, and simulated live.
AXI-Lite Interconnect
Two masters arbitrating a shared AXI4-Lite bus to two slaves, generated and verified end to end, then simulated live with rendered waveforms.
Pipelined RV32I Core
A 3-stage RISC-V pipeline with a register file, ALU, decoder, and hazard forwarding, generated and verified end to end.
DRAM Controller
A single-bank DRAM controller with a refresh counter, a bank state machine, and command timing, generated and verified end to end.